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[Other] S3C44B0X中文技术文档

Description:

 

介    绍
三星的S3C44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。
S3C44B0X提供以下配置：2.5V ARM7TDMI 内核带有8Kcache ;可选的internal SRAM;LCD Controller(最大支持256色STN，使用LCD专用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO； 2-ch general DMAs / 2-ch peripheral DMAs with external request pins； External memory controller (chip select logic, FP/ EDO/SDRAM controller)； 5-ch PWM timers & 1-ch internal timer；Watch Dog Timer；71 general purpose I/O ports / 8-ch external interrupt source； RTC with calendar function； 8-ch 10-bit ADC； 1-ch multi-master IIC-BUS controller； 1-ch IIS-BUS controller； Sync. SIO interface and On-chip clock generator with PLL.。
S3C44B0X采用一种新的三星ARM CPU嵌入总线结构-SAMBA2，最大达66MHZ。

Platform: | Size: 78690 | Author: ssunshine | Hits:

[Windows CE] Pccard

Description: pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.-pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
Platform: | Size: 27648 | Author: makku | Hits:

[Windows Develop] Arca2Core

Description: Arca2的规格文档，一种RISC结构CPU。-Arca2 specification documents, a RISC structure of CPU.
Platform: | Size: 914432 | Author: 牟刚 | Hits:

[Software Engineering] W90P710CD_CDGf

Description: The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI Risc processor
Platform: | Size: 3402752 | Author: liuxy204 | Hits:

[assembly language] cpudesheji

Description: CPUname是RISC处理器，采用普林斯顿体系结构，CPU与数据存储器间的通信使用Load/Store指令实现，数据存储采取统一的32位字长格式，32位定长指令，地址指令格式。使用专用数据通路结构，四级流水线，分为取指及译码，取数，运算，回写四步，拥有相关专用通路以解决数据相关问题,对跳转指令应用分支预测技术，使其不影响流水。-CPUname is a RISC processor, using the Princeton architecture, CPU and data memory, the communication between the use of Load/Store instruction implementation, data storage to a unified format, 32-bit word length, 32-bit fixed-length instructions, the address instruction format. Using a dedicated data path structure, four lines, is divided into fetching and decoding, take the number of operations, write-back four-step, with related specialty channels to address the data-related problems, and jump instructions use branch prediction techniques, so as not to affect the water.
Platform: | Size: 8875008 | Author: 张晓风 | Hits:

[Other Embeded program] 1

Description: HCS12X微控制器系列是HCS12系列的升级版，XGate外围处理器又是其重要的组成原件。XGATE是一款能够独立运行在主CPU上的可编程内核，可以匹配所有S12终端以及RISC设备。本篇应用比价就介绍了如何配置以及使用XGATE。-HCS12X micro-controller family is the HCS12 series of upgrades, XGate external processor is also an important component of its original. XGATE is a main CPU can be run independently on a programmable core, you can match all S12 devices, as well as RISC devices. This application describes how to configure the parity and the use of XGATE.
Platform: | Size: 314368 | Author: laker | Hits:

[VHDL-FPGA-Verilog] mips

Description: cpu---risc---mips源代码-cpu---risc---mips
Platform: | Size: 3072 | Author: mhjohnson | Hits:

[SCM] ourdev_441156

Description: AVR单片机是1997年由ATMEL公司研发出的增强型内置Flash的RISC(Reduced Instruction Set CPU) 精简指令集高速8位单片机。AVR的单片机可以广泛应用于计算机外部设备、工业实时控制、仪器仪表、通讯设备、家用电器等各个领域。-AVR Microcontroller ATMEL Corporation in 1997 developed by the enhanced built-in Flash of the RISC (Reduced Instruction Set CPU) high-speed 8-bit RISC microcontroller. AVR microcontroller can be widely used in computer peripherals, industrial real-time control, instrumentation, communications equipment, household appliances and other fields.
Platform: | Size: 2150400 | Author: 花自涛 | Hits:

[VHDL-FPGA-Verilog] cpu16

Description: 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code
Platform: | Size: 182272 | Author: peterloo | Hits:

[VHDL-FPGA-Verilog] Verilog-HDLTOP-DOWN

Description: 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
Platform: | Size: 43008 | Author: 刘鹏飞 | Hits:

[VHDL-FPGA-Verilog] sparc_verilog

Description: open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
Platform: | Size: 214016 | Author: 王翔 | Hits:

[VHDL-FPGA-Verilog] simplesim-3v0e

Description: SimpleScalar 模拟器模拟的是一个超标量，5级流水的RISC体系结构的CPU模型，提供了从最简单到超标量乱序发射的不同的模拟程序。sim-outorder 是一个具有完整功能的模拟程序。在sim-outorder中使用了几乎所有的模拟资源，在阅读代码之前对模拟的体系结构和模拟资源充分的了解，能够大大提高下一步工作的效率。-SimpleScalar tool
Platform: | Size: 4420608 | Author: zhaoyan | Hits:

[VHDL-FPGA-Verilog] mips_project

Description: 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
Platform: | Size: 17408 | Author: yangxinghua | Hits:

[SCM] smdk2413_application_note_rev10

Description: SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-bit RISC (ARM926EJ-S) CPU core, separate 8KB instruction and 8KB data cache, MMU to handle virtual memory management, LCD controller (STN & TFT), NAND flash boot loader, System Manager (chip select logic and SDRAM controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O ports, RTC, 8-ch 10-bit ADC and touch screen interface, IIC-BUS interface, IIS-BUS interface, USB host, USB device, SD host & multimedia card interface, ATA Interface, IrDA, Camera Interface, Watch Dog Timer, 2-ch SPI and PLL for clock generation. The SMDK2413 consists of S3C2413X, boot EEPROM (flash ROM), SDRAM, LCD interface, two serial communication ports, configuration switches, JTAG interface and status LEDs.
Platform: | Size: 2135040 | Author: fateme | Hits:

[VHDL-FPGA-Verilog] VHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

[SCM] Code-Vision-AVR-C-11

Description: AVR 单片机的C语言例程 一共有30多个，基本通用-AVR RISC(Reduced Instruction Set CPU
Platform: | Size: 77824 | Author: AK47 | Hits:

[Driver Develop] arm-gcc-3.4.4-gm8180.tar.bz2

Description: GM’s GM8180 MDC1 hardware environment is a highly efficient RISC-based platform for the purpose of verifying and evaluating AMBA-based designs in the early development stage. The complete set of MDC1 GM8180 platform consists of a main board (MB120) equipped with GM8180 chip and an embedded GM FA626 CPU.-Hardware: Intel x86 compatible PC Standard 16550 UART Software: Standard Linux distribution (Fedora core 2.6.14-FC5 or above) FA626-based Linux distribution
Platform: | Size: 54044672 | Author: 北科 | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: 1. RISC工作每执行一条指令需要八个时钟周期。RISC的复位和启动通过rst控制，rst高电平有效。Rst为低时，第一个fetch到达时CPU开始工作从Rom的000处开始读取指令，前三个周期用于读指令。 在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备 对总线写操作时，在第3.5个时钟周期处，建立写的地址，第4个时钟周期输出数据，第5个时钟周期输出写信号。至第6个时钟结束，第7.5时钟地址输出PC地址，为下一个指令周期做好准备。 2. 操作过程：新建工程，编译compile all，然后仿真，在wave窗口加入要观察的信号，然后run –all，结束时完成test1的测试，重复两次run –all完成test2，test3的波形仿真。 -1. RISC work every eight clock cycles to execute an instruction needs. RISC reset and start by rst control, rst active high. Rst is low, the first CPUs fetch arrives starting from Rom s 000 start reading instruction, the first three cycles for reading instruction. When the read operation is performed on the bus, at 3.5 cycles, memory, or port address output to the address bus, 4- 6 clock cycles, and the read signal rd, read data to the bus, a logic operation. 7 clock cycles, rd invalid, 7.5 PC clock address output address, ready for the next instruction The write operation on the bus, in Section 3.5 of the clock cycle, to establish a write address, and four clock cycles and output data, the fifth clock cycle output write signal. To the end of the six clock the 7.5 clock address output PC address, ready for the next instruction cycle. Operation: new construction, the compiler compile all, and simulation, join in the wave window to observe the signal, then the run-all completed by the
Platform: | Size: 1026048 | Author: 宋颖 | Hits:

[Software Engineering] ca01

Description: The Computer Architecture Lecture Notes. It includes general information about CPU and MIPS. Also, It mentions about RISC and CISC microprocessor.
Platform: | Size: 683008 | Author: niziplimali | Hits:

[Software Engineering] tx79architecture

Description: Toshiba TX System RISC TX79 Core Architecture (Symmetric 2-way superscalar 64-bit CPU) Rev. 2.0 This user’s manual describes the C790 superscalar microprocessor for the system designer, paying special attention to the software interface and the bus interface.
Platform: | Size: 3470336 | Author: | Hits:
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